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| ds-25dn256?039b?5/2014 features ? single 2.3v - 3.6v supply ? serial peripheral inte rface (spi) compatible ? supports spi modes 0 and 3 ? supports dual output read ? 104mhz maximum operating frequency ? clock-to-output (t v ) of 6ns ? flexible, optimized erase architecture for code + data storage applications ? uniform 256-byte page erase ? uniform 4-kbyte block erase ? uniform 32-kbyte block erase ? full chip erase ? hardware controlled locking of protected sectors via wp pin ? 128-byte programmable otp security register ? flexible programming ? byte/page program (1 to 256 bytes) ? fast program and erase times ? 1.5ms typical page program (256 bytes) time ? 40ms typical 4-kbyte block erase time ? 320ms typical 32-kbyte block erase time ? automatic checking and reporting of erase/program failures ? software controlled reset ? jedec standard manufacturer and device id read methodology ? low power dissipation ? 350na ultra deep power down current (typical) ? 5a deep power-down current (typical) ? 25ua standby current (typical) ? 6ma active read current (typical) ? endurance: 100,000 pr ogram/erase cycles ? data retention: 20 years ? complies with full industrial temperature range ? industry standard green (pb/halide-fr ee/rohs compliant) package options ? 8-lead soic (150-mil) ? 8-pad ultra thin dfn (2 x 3 x 0.6mm) ? 8-lead tssop package at25dn256 256-kbit, 2.3v minimum spi serial flash memory with dual-read support preliminary datasheet
2 at25dn256 ds-25dn256?039b?5/2014 1. description the adesto ? at25dn256 is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from flas h memory into embedded or external ram for execution. the flexible erase architecture of the at25dn256, with its page erase granularity it is ideal for data storage as well, eliminating the need for additional data storage devices. the erase block sizes of the at25dn256 have been optimized to meet the needs of today's code and data storage applications. by optimizing the size of the erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. this increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall devic e density. the device also contains a specialized otp (one-time programmabl e) security register that can be used for purposes such as unique device serialization, system-level electronic se rial number (esn) storage, locked key storage, etc. specifically designed for use in many different systems, t he at25dn256 supports read, program, and erase operations with a wide supply voltage range of 2.3v to 3.6v. no separ ate voltage is required for programming and erasing. 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally be placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedance state. when the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an operation, and a low-to-high transition is required to end an operation. when ending an in ternally self-timed operation such as a program or erase cycle, the device will not enter the sta ndby mode until the completion of the operation. low input sck serial clock: this pin is used to provide a clock to t he device and is used to control the flow of data to and from the device. command, address, a nd input data present on the si pin is always latched in on the rising edge of sck, while output data on the so pin is always clocked out on the falling edge of sck. - input si (i/o 0 ) serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched in on the rising edge of sck. with the dual-output read commands, th e si pin becomes an output pin (i/o 0 ) in conjunction with other pins to allow two bits of data on (i/o 1-0 ) to be clocked out on every falling edge of sck. to maintain consistency with the spi nomenclature, the si (i/o 0 ) pin will be referenced as the si pin unless specifically addressing the dual-i/o modes in which case it will be referenced as i/o 0. data present on the si pin will be ignored whenever the device is deselected (cs is deasserted). - input/ output so (i/o 1 ) serial output: the so pin is used to shift data out from the device. data on the so pin is always clocked out on the falling edge of sck. with the dual-output read commands, the so pin remains an output pin (i/o 1 ) in conjunction with other pins to allow two bits of data on (i/o 1-0 ) to be clocked out on every falling edge of sck. to maintain consistency with t he spi nomenclature, the so (i/o 1 ) pin will be referenced as the so pin unless specifically addressing the dual-i/o modes in which case it will be referenced as i/o 1. the so pin will be in a high-impedance state whenever the device is deselected (cs is deasserted). - input/ output 3 at25dn256 ds-25dn256?039b?5/2014 wp write protect: the wp pin controls the hardware locking feature of the device. please refer to ?protection commands and features? on page 12 for more details on protection features and the wp pin. the wp pin is internally pulled-high and may be left floating if hardware c ontrolled protection will not be used. however, it is recommended that the wp pin also be externally connected to v cc whenever possible. low input hold hold: the hold pin is used to temporarily pause se rial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a program or erase cycle. please refer to ?hold? on page 26 for additional details on the hold operation. the hold pin is internally pulled-high and may be left floating if the hold function will not be used. however, it is recommended that the hold pin also be externally connected to v cc whenever possible. low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. - power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. - power table 2-1. pin descriptions (continued) symbol name and function asserted state type table 2-2. pinouts figure 2-1. 8-soic top view figure 2-2. 8-tssop top view figure 2-3. 8-udfn (top view) 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si cs so wp gnd 1 2 3 4 8 7 6 5 vcc hold sck si 4 at25dn256 ds-25dn256?039b?5/2014 ) / $ 6 + 0 ( 0 2 5 < $ 5 5 $ < < * $ 7 , 1 * & 6 6 & . 6 2 6 , , 2 < ' ( & 2 ' ( 5 $ ' ' 5 ( 6 6 / $ 7 & + ; ' ( & 2 ' ( 5 , 2 % 8 ) ) ( 5 6 $ 1 ' / $ 7 & + ( 6 & 2 1 7 5 2 / $ 1 ' 3 5 2 7 ( & 7 , 2 1 / 2 * , & 6 5 $ 0 ' $ 7 $ % 8 ) ) ( 5 : 3 , 1 7 ( 5 ) $ & ( & 2 1 7 5 2 / $ 1 ' / 2 * , & + 2 / ' 3. block diagram figure 3-1. block diagram 5 at25dn256 ds-25dn256?039b?5/2014 4. memory array to provide the greatest flexibility, the memory array of the at25dn256 can be erased in three levels of granularity including a full chip erase. the size of the erase blocks is optimized for both code and data storage applications, allowing both code and data segments to reside in their own erase regions. the memory architecture diagram illustrates the breakdown of each erase level. figure 4-1. memory architecture diagram 5. device operation the at25dn256 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the spi master. the spi master communicates with the at25dn256 via the spi bus which is comprised of four signal lines: chip select (cs ), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at25dn256 supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 5.1 dual output read the atx features a dual-output read mode that allow two bits of data to be clocked out of the device every clock cycle to improve throughput. to accomplish this, both the si and so pins are utilized as outputs for the transfer of data bytes. with the dual-output read array command, the si pin becomes an output along with the so pin. 32kb 4kb 1-256 byte block erase block erase page program (52h command) (20h command) (02h command) 4kb 007fffh ? 007000h 256 bytes 007fffh ? 007f00h 4kb 006fffh ? 006000h 256 bytes 007effh ? 007e00h 4kb 005fffh ? 005000h 256 bytes 007dffh ? 007d00h 4kb 4kb 4kb 002fffh ? 002000h 256 bytes 0002ffh ? 000200h 4kb 001fffh ? 001000h 256 bytes 0001ffh ? 000100h 4kb 000fffh ? 000000h 256 bytes 0000ffh ? 000000h 004fffh ? 004000h 003fffh ? 003000h block erase detail page program detail page address block address range range 32kb ? ? ? sck cs si so msb lsb msb lsb 6 at25dn256 ds-25dn256?039b?5/2014 6. commands and addressing a valid instruction or operation must always be started by first asserting the cs pin. after the cs pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the host controller. all opcode, address, and data bytes are transferred with the most-significant bi t (msb) first. an operation is ended by deasserting the cs pin. opcodes not supported by the at25dn256 will be ignored by t he device and no operation will be started. the device will continue to ignore any data presented on the si pin until the start of the next operation (cs pin being deasserted and then reasserted). in addition, if the cs pin is deasserted before complete opcode and address information is sent to the device, then no operation will be performed and the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23-a0. since the upper address limit of the 256 memory array is 00ffffh, address bits a23-a16 are always ignored by the device. table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 up to 104mhz 3 1 1+ 03h 0000 0011 up to 33mhz 3 0 1+ dual output read 3bh 0011 1011 up to 50mhz 3 1 1+ program and erase commands page erase 81h 1000 0001 up to 104mhz 3 0 0 block erase (4 kbytes) 20h 0010 0000 up to 104mhz 3 0 0 block erase (32 kbytes) 52h 0101 0010 up to 104mhz 3 0 0 d8h 1101 1000 up to 104mhz 3 0 0 chip erase 60h 0110 0000 up to 104mhz 0 0 0 c7h 1100 0111 up to 104mhz 0 0 0 chip erase (legacy command) 62h 0110 0010 up to 104mhz 0 0 0 byte/page program (1 to 256 bytes) 02h 0000 0010 up to 104mhz 3 0 1+ protection commands write enable 06h 0000 0110 up to 104mhz 0 0 0 write disable 04h 0000 0100 up to 104mhz 0 0 0 security commands program otp security register 9bh 1001 1011 up to 104mhz 3 0 1+ read otp security register 77h 0111 0111 up to 104mhz 3 2 1+ status register commands read status register 05h 0000 0101 up to 104mhz 0 0 1+ write status register byte 1 01h 0000 0001 up to 104mhz 0 0 1 7 at25dn256 ds-25dn256?039b?5/2014 7. read commands 7.1 read array the read array command can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address is specified. the device incorporates an internal address counter that automatically increments every clock cycle. two opcodes (0bh and 03h) can be used for the read array command. the use of each opcode depends on the maximum clock frequency that will be used to read data from the device. the 0bh opcode can be used at any clock frequency up to the maximum specified by f clk , and the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. following the three address bytes, an additional dummy byte needs to be clocked into the device if the 0bh opcode is used for the read array operation. after the three address bytes (and the dummy byte if us ing opcode 0bh) have been clocked in, additional clock cycles will result in data being output on the so pin. the data is always output with the msb of a byte first. when the last byte (00ffffh) of the memory array has been read, the devic e will continue reading back at the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into high-impedance state. the cs pin can be deasserted at any time and does not require a full byte of data be read. figure 7-1. read array - 03h opcode write status register byte 2 31h 0011 0001 up to 104mhz 0 0 1 miscellaneous commands reset f0h 1111 0000 up to 104mhz 0 0 1 (d0h) read manufacturer and device id 9fh 1001 1111 up to 104mhz 0 0 1 to 4 read id (legacy command) 15h 0001 0101 up to 104mhz 0 0 2 deep power-down b9h 1011 1001 up to 104mhz 0 0 0 resume from deep power-down abh 1010 1011 up to 104mhz 0 0 0 ultra deep power-down 79h 0111 1001 up to 104mhz 0 0 0 table 6-1. command listing command opcode clock frequency address bytes dummy bytes data bytes sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte 1 high-impedance 8 at25dn256 ds-25dn256?039b?5/2014 figure 7-2. read array - 0bh opcode 7.2 dual-output read array the dual-output read array command is similar to the standard read array command and can be used to sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has been specified. unlike the standard read array command, however, the dual-output read array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one. the dual-output read array command can be used at any clock frequency, up to the maximum specified by f rddo . to perform the dual-output read array operation, the cs pin must first be asserted and then the opcode 3bh must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. following the three address bytes, a single dummy byte must also be clocked into the device. after the three address bytes and the dummy byte have been cl ocked in, additional clock cycles will result in data being output on both the so and sio pins. the data is always output with the msb of a byte first and the msb is always output on the so pin. during the first clock cycle, bit seven of the first data byte is output on the so pin, while bit six of the sam e data byte is output on the sio pin. during the next clock cycle, bits five and four of the first data byte are output on the so and sio pins, respectively. the sequence continues with each byte of data being output after every four clock cycles. when the last byte (fffffh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array.deasserting the cs pin will terminate the read operation and put the so and sio pins into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-3. dual-output read array k s i o msb msb 23 1 0 00001011 67 5 41011 9 812 394243 41 40 37 38 33 36 35 34 31 32 29 30 44 47 48 46 45 opcode aaaa aaa a a msb xxxxxxx x msb msb ddddddd d d d address bits a23-a0 don't care data byte 1 high-impedance 6 & . & 6 6 , 6 , 2 6 2 0 6 % 0 6 % 2 3 & 2 ' ( $ $ $ $ $ $ $ $ $ 0 6 % ; ; ; ; ; ; ; ; 0 6 % 0 6 % 0 6 % ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' $ ' ' 5 ( 6 6 % , 7 6 $ $ ' 2 1 7 & $ 5 ( 2 8 7 3 8 7 ' $ 7 $ % < 7 ( 2 8 7 3 8 7 ' $ 7 $ % < 7 ( + , * + , 0 3 ( ' $ 1 & ( 9 at25dn256 ds-25dn256?039b?5/2014 8. program and erase commands 8.1 byte/page program the byte/page program command allows anywhere from a singl e byte of data to 256 bytes of data to be programmed into previously erased memory locations. an erased memory location is one that has all eight bits set to the logical ?1? state (a byte value of ffh). before a byte/page program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 12 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte/page program command, an opcode of 02h mu st be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer. if the starting memory address denoted by a23-a0 does not fall on an even 256-byte page boundary (a7-a0 are not all 0), then special circumstances regarding which memory locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page. for example, if the starting address denoted by a23-a0 is 0000feh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000feh and 0000ffh while the last byte of data will be programmed at address 000000h. the remaining bytes in the page (addresses 000001h through 0000fdh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate memory array locations based on the starting addr ess specified by a23-a0 and the number of data bytes sent to the device. if less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not be programmed and will remain in the erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t pp or t bp if only programming a single byte. the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and no data will be programmed into the memory array. in addition, if the memory is in the protected state (see ?block protection? on page 13 ), then the byte/page program command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin not being deasserted on byte boundaries, or because the memory location to be programmed is protected. while the device is programming, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp or t pp time to determine if the data bytes have finished programming. at some point before the program cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent programming algorit hm that can detect when a byte location fails to program properly. if a programming error arises, it will be i ndicated by the epe bit in the status register. 10 at25dn256 ds-25dn256?039b?5/2014 figure 8-1. byte program figure 8-2. page program 8.2 page erase the page erase command can be used to individually erase any page in the main memory array. the main memory byte/page program command can be utilized at a later time. to perform a page erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device followed by three address bytes comprised of eight dummy bits, 8 page address bits (pa7 - pa0) that specify the page in the main memory to be erased, and eight dummy bits. when a low-to-high transition occurs on the cs pin, the device will erase the selected page (the erased state is a logic 1). the erase operation is internally self-timed and should take place in a maximum time of t pe . during this time, the rdy /busy bit in the status register will indicate that the device is busy. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly. if an erase error arises, it will be indicated by the epe bit in the status register. 8.3 block erase a block of 4 or 32 kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of three different opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, and an opcode of 52h or d8h is used for a 32-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bi t of the status register to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h, or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4- or 32-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the device will erase the appropriate block. the erasing of the block is internally self-timed and should take place in a time of t blke . sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in sck cs si so msb msb 23 1 0 00000010 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n 11 at25dn256 ds-25dn256?039b?5/2014 since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the device. therefore, for a 4-kbyte erase, address bits a11-a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14-a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operat ion and no erase operation will be performed. if the memory is in the protected state, then the block erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent, the cs pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-3. block erase 8.4 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. three opcodes (60h, 62h, and c7h) can be used for the chip erase command. there is no difference in device functionality when utilizing the three opcodes, so they can be used interchangeably. to perform a chip erase, one of the three opcodes must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of t he device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. in addition, if the memory array is in the protected state, then the chip erase command will not be executed, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the cs pin is deasserted on uneven byte boundaries or if the memory is in the protected state. while the device is executing a successful erase cycle, the status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t chpe time to sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance 12 at25dn256 ds-25dn256?039b?5/2014 determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. the device also incorporates an intelligent erase algorithm t hat can detect when a byte location fails to erase properly. if an erase error occurs, it will be indicated by the epe bit in the status register. figure 8-4. chip erase 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status register to a logical ?1? state. the wel bit must be set before a byte/page program, erase, program otp security register, or write status register command can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bit in the status register is not set prior to the issuance of one of these commands, then the command will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-1. write enable sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance 13 at25dn256 ds-25dn256?039b?5/2014 9.2 write disable the write disable command is used to reset the write enable lat ch (wel) bit in the status register to the logical ?0? state. with the wel bit reset, all byte/page program, erase, program otp security register, and write status register commands will not be executed. other conditions can also caus e the wel bit to be reset; for more details, refer to the wel bit section of the status register description. to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0?. the complete opcode must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable 9.3 block protection the device can be software protected against erroneous or ma licious program or erase operations by utilizing the block protection feature of the device. block protection can be enabled or disabled by using the write status register command to change the value of the block protection (bp0) bit in the status register. the following table outlines the two states of the bp0 bit and the associated protection area. when the bp0 bit of the status register is in the logical ?1? state, the entire memory array will be protected against program or erase operations. any attempts to send a byte /page program command, a block erase command, or a chip erase command will be ignored by the device. as a safeguard against accidental or erroneous protecting or u nprotecting of the memory array, the bp0 bit itself can be locked from updates by using the wp pin and the bpl (block protection locked) bit of the status register (see ?protected states and the write protect pin? on page 14 for more details). the bp0 bit of the status register is a nonvolatile bit; ther efore, the bp0 bit will retain its state even after the device has been power cycled. care should be taken to ensure that bp0 is in the logical ?1? state before powering down for those applications that wish to have the memory array fully protected upon power up. the default state for bp0 when shipped from adesto is ?0?. sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance table 9-1. memory array protection protection level bp0 protected memory address none 0 none full memory 1 00000h - 00ffffh 14 at25dn256 ds-25dn256?039b?5/2014 9.4 protected states and the write protect pin the wp pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array. instead, the wp pin, in conjunction with the bpl (block protection locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the wp pin must be asserted and the bpl bit must be in the logical ?1? state. when hardware locking is active, the block protection (bp0) bit is locked and the bpl bit itself is also locked. therefore, if the memory array is protected, it will be locked in the protected state, and if the memory array is unprotected, it will be locked in the unprotected state. these states cannot be changed as long as hardware locking is active, so the write status register command will be ignored. in order to modify the protection status of the memory array, the wp pin must first be deasserted, and the bpl bit in the status register must be reset back to the logical ?0? state using the write status register command. if the wp pin is permanently connected to gnd, then once the bpl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sector s can be unprotected and protected as needed and then hardware locked at a later time by simply setting the bpl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to v cc , the bpl bit in the status register can be set to a logical ?1?, but doing so will not lock the bp0 bit. table 9-2 details the various protection and locking states of the device. 10. security commands 10.1 program otp security register the device contains a specialized otp (one-time programmabl e) security register that can be used for purposes such as unique device serialization, system-level electronic serial number (esn) storage, locked key storage, etc. the otp security register is independent of the main flash memory array and is comprised of a total of 128 bytes of memory divided into two portions. the first 64 bytes (byte locations 0 th rough 63) of the otp security register are allocated as a one-time user-programmable space. once these 64 bytes have been programmed, they cannot be erased or reprogrammed. the remaining 64 bytes of the otp security register (byte locations 64 through 127) are factory programmed by adesto and will contain a unique value fo r each device. the factory programmed data is fixed and cannot be changed. table 9-2. hardware and software locking wp bpl locking bpl change allowed bp0 and protection status 0 0 can be modified from 0 to 1 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unpr otected freely. 0 1 hardware locked locked bp0 bit locked in current state. the write status register command will have no affect. memory array is locked in current protected or unprotected state. 1 0 can be modified from 0 to 1 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unpr otected freely. 1 1 can be modified from 1 to 0 bp0 bit unlocked and modifiable using the write status register command. memory array can be protected and unpr otected freely. 15 at25dn256 ds-25dn256?039b?5/2014 the user-programmable portion of the otp security regist er does not need to be erased before it is programmed. in addition, the program otp security register command operates on the entire 64-byte user-programmable portion of the otp security register at one time. once the user-progr ammable space has been programmed with any number of bytes the user-programmable space cannot be pr ogrammed again; therefore, it is not possible to only program the first two bytes of the register and then program the remaining 62 bytes at a later time. before the program otp security register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to program the otp security register, the cs pin must first be asserted and an opcode of 9bh must be clocked into the device followed by the three address bytes denoting the first byte location of the otp security regist er to begin programming at. since the size of the user- programmable portion of the otp security register is 64 bytes, the upper order address bits do not need to be decoded by the device. therefore, address bits a23-a6 will be ignored by the device and thei r values can be either a logical ?1? or ?0?. after the address bytes have been clocked in, data can then be clocked into the device and will be stored in the internal buffer. if the starting memory address denoted by a23-a0 does not start at the beginning of the otp security register memory space (a5-a0 are not all 0), then special circumstances regarding which otp security register locations to be programmed will apply. in this situation, any data that is sent to the device that goes beyond the end of the 64-byte user- programmable space will wrap around back to the beginning of t he otp security register. for example, if the starting address denoted by a23-a0 is 00003eh, and three bytes of data are sent to the device, then the first two bytes of data will be programmed at otp security register addresses 00003eh and 00003fh while the last byte of data will be programmed at address 000000h. the remaining bytes in the otp security register (addresses 000001h through 00003dh) will not be programmed and will remain in the erased state (ffh). in addition, if more than 64 bytes of data are sent to the device, then only the last 64 bytes sent will be latched into the internal buffer. when the cs pin is deasserted, the device will take the data stored in the internal buffer and program it into the appropriate otp security register locations based on the starting address specified by a23-a0 and the number of data bytes sent to the device. if less than 64 bytes of data were sent to the device, then the remaining bytes within the otp security register will not be programmed and will remain in t he erased state (ffh). the programming of the data bytes is internally self-timed and should take place in a time of t otpp . the three address bytes and at least one complete byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation and the user-programmable portion of t he otp security register will not be programmed. the wel bit in the status register will be reset back to the logica l ?0? state if the otp security register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, the cs pin being deasserted on uneven byte boundaries, or because the user-progr ammable portion of the otp security register was previously programmed. while the device is programming the otp security register, th e status register can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t otpp time to determine if the data bytes have finished programming. at some point before the otp security register programming completes, the wel bit in the status register will be reset back to the logical ?0? state. if the device is powered-down during the otp security register program cycle, then the contents of the 64-byte user programmable portion of the otp security regist er cannot be guaranteed and cannot be programmed again. table 10-1. otp security register security register byte number 0 1 . . . 62 63 64 65 . . . 126 127 one-time user programmable factory programmed by adesto 16 at25dn256 ds-25dn256?039b?5/2014 the program otp security register command utilizes the inte rnal 256-buffer for processing. therefore, the contents of the buffer will be altered from its previous state when this command is issued. figure 10-1. program otp security register 10.2 read otp security register the otp security register can be sequentially read in a similar fashion to the read array operation up to the maximum clock frequency specified by f clk . to read the otp security register, the cs pin must first be asserted and the opcode of 77h must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the otp security register. following the three address bytes, two dummy bytes must be clocked into the device before data can be output. after the three address bytes and the dummy bytes have been cl ocked in, additional clock cycles will result in otp security register data being output on the so pin. when the last byte (00007fh) of the otp security register has been read, the device will continue reading back at the beginni ng of the register (000000h). no delays will be incurred when wrapping around from the end of the regist er to the beginning of the register. deasserting the cs pin will terminate the read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 10-2. read otp security register sck cs si so msb msb 23 1 0 10011011 67 5 49 839 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aa aaa a msb ddddddd d address bits a23-a0 data in byte 1 msb ddddddd d data in byte n sck cs si so msb msb 23 1 0 01110111 67 5 41011 9 812 3336 35 34 31 32 29 30 opcode aaaa aaa a axx x msb msb ddddddd d d d address bits a23-a0 msb xxxxx x don't care data byte 1 high-impedance 17 at25dn256 ds-25dn256?039b?5/2014 11. status register commands 11.1 read status register the status register can be read to determine the device?s r eady/busy status, as well as the status of many other functions such as hardware locking and block protection. t he status register can be read at any time, including during an internally self-timed program or erase operation. the status register consists of two bytes. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of status register byte 2 has been clocked out, the sequence will repeat itself, starting again with bit 7 of status register byte 1, as long as the cs pin remains asserted and the clock pin is being pulsed. the data in the status register is constantly being updated, so each repeating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. 11.1.1 bpl bit the bpl bit is used to control whether the block protection (bp0) bit can be modified or not. when the bpl bit is in the logical ?1? state a nd the wp pin is asserted, the bp0 bit will be locked and cannot be modified. the memory array will be locked in the current protected or unprotected state. when the bpl bit is in the logical ?0? state, the bp0 bit wi ll be unlocked and can be modified. the bpl bit defaults to the logical ?0? state after device power-up. table 11-1. status register format bit (1) 1. only bits 7 and 2 of the status register can be modified when using the write status register command. name type (2) 2. r/w = readable and writable ? r = readable only description 7 bpl block protection locked r/w 0 bp0 bit unlocked (default). 1 bp0 bit locked in current state when wp asserted. 6 res reserved for future use r 0 reserved for future use. 5 epe erase/program error r 0 erase or program operation was successful. 1 erase or program error detected. 4 wpp write protect (wp ) pin status r 0 wp is asserted. 1 wp is deasserted. 3 res reserved for future use r 0 reserved for future use. 2 bp0 block protection r/w 0 entire memory array is unprotected. 1 entire memory a rray is protected. 1 wel write enable latch status r 0 device is not write enabled (default). 1 device is write enabled. 0 rdy /bsy ready/busy status r 0 device is ready. 1 device is busy with an internal operation. 18 at25dn256 ds-25dn256?039b?5/2014 the bpl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the bpl bit may only be changed from a logical ?0? (bp0 bit unlocked) to a logical ?1? (bp0 bit locked). in order to reset the bpl bit back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the bpl and bp0 bits are the only bits of the status register that can be user modified via the write status register command. 11.1.2 epe bit the epe bit indicates whether the last erase or program operation completed successfully or not. if at least one byte during the erase or program operation did not erase or program properly, then the epe bit will be set to the logical ?1? state. the epe bit will not be set if an erase or program operat ion aborts for any reason such as an attempt to erase or program the memory when it is protected or if the wel bit is not set prior to an erase or program operation. the epe bit will be updated after every erase and program operation. 11.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 11.1.4 bp0 bit the bp0 bits provides feedback on the software protection status for the device. i n addition, the bp0 bit can also be modified to change the state of the software protection to allow the entire memory array to be protected or unprotected. when the bp0 bit is in the logical ?0? state, then the entire memory array is unprotected. when the bp0 bit is in the logical ?1? state, then the entire memory array is protected against program and erase operations. 11.1.5 wel bit the wel bit indicates the current status of the internal writ e enable latch. when the wel bit is in the logical ?0? state, the device will not accept any byte/page program, erase, program otp security register, or write status register commands. the wel bit defaults to the logical ?0? state afte r a device power-up or reset oper ation. in addition, the wel bit will be reset to the logical ?0? state automatically under the following conditions: ? write disable operation completes successfully ? write status register operation completes successfully or aborts ? program otp security register operation completes successfully or aborts ? byte/page program operation completes successfully or aborts ? block erase operation completes successfully or aborts ? chip erase operation completes successfully or aborts ? hold condition aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete o r unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode fo r a byte/page program, erase, program otp security register, or write status register co mmand must have been clocked into the device. 11.1.6 rdy /bsy bit the rdy /bsy bit is used to determine whether or not an internal oper ation, such as a program or erase, is in progress. to poll the rdy /bsy bit to detect the completion of a program or erase cycle, new status register data must be continually clocked out of the device until the state of the rdy /bsy bit changes from a logical ?1? to a logical ?0?.note that the rdy /bsy bit can be read either from status regist er byte 1 or from status register byte 2. 19 at25dn256 ds-25dn256?039b?5/2014 11.1.7 rste bit the rste bit is used to enable or disable the reset command . when the rste bit is in the logical 0 state (the default state after power-up), the reset command is disabled and any attempts to reset the device using the reset command will be ignored. when the rste bit is in the logical 1 state, the reset command is enabled. the rste bit will retain its state as long as power is applied to the device. once set to the logical 1 state, the rste bit will remain in that state until it is modified using the write status register byte 2 command or until the device has been power cycled. the reset command itself will not change the state of the rste bit. note: 1. only bits 4 and 3 of status register byte 2 will be modified when using the write status ? register byte 2 command 2. r/w = readable and writeable ? r = readable only. figure 11-1. read status register ? 11.2 write status register the write status register command is used to modify the bpl bit and the bp0 bit of the status register. before the write status register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device followed by one byte of data. the one byte of data consists of the bpl bit value, four don?t care bits, the table 11-2. status register format ? byte 2 bit (1) name type (2) description 7 res reserved for future use r 0 reserved for future use 6 res reserved for future use r 0 reserved for future use 5 res reserved for future use r 0 reserved for future use 4 rste reset enabled r/w 0 reset command is disabled (default) 1 reset command is enabled 3 res reserved for future use r 0 reserved for future use 2 res reserved for future use r 0 reserved for future use 1 res reserved for future use r 0 reserved for future use 0 rdy /bsy ready/busy status r 0 device is ready 1 device is busy with an internal operation sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd dd d d msb dddddd d d status register byte1 status register byte2 high-impedance 20 at25dn256 ds-25dn256?039b?5/2014 bp0 bit value, and two additional don?t care bits (see table 11-3 ). any additional data bytes that are sent to the device will be ignored. when the cs pin is deasserted, the bpl bit and the bp0 bit in the status register will be modified, and the wel bit in the status register will be reset back to a l ogical ?0?. the value of bp0 and the state of the bpl bit and the wp pin before the write status register command was executed (the prior state of the bpl bit and the state of the wp pin when the cs pin is deasserted) will determine whether or not software protection will be changed. please refer to section 9.4, ?protected states and the write protect pin? on page 14 for more details. the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the bpl and bp0 bits will not change, memory protection status will not change, and the wel bit in the status register will be reset back to the logical ?0? state. if the wp pin is asserted, then the bpl bit can only be set to a logical ?1?. if an attempt is made to reset the bpl bit to a logical ?0? while the wp pin is asserted, then the write status register byte command will be ignored, and the wel bit in the status register will be reset back to the logical ?0? state. in order to reset the bpl bit to a logical ?0?, the wp pin must be deasserted. figure 11-2. write status register 11.3 write status register byte 2 the write status register byte 2 command is used to modi fy the rste. using the write status register byte 2 command is the only way to modify the rste in the status register during normal device operation. before the write status register byte 2 command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical 1. to issue the write status register byte 2 command, the cs pin must first be asserted and then the opcode 31h must be clocked into the device followed by one byte of data. the one byte of data consists of three don?t-care bits, the rste bit value, and four additional don?t-care bits (see table 11-4 ). any additional data bytes sent to the device will be ignored. when the cs pin is deasserted, the rste bit in the status regist er will be modified, and the wel bit in the status register will be reset back to a logical 0. table 11-3. write status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bpl x x x x bp0 x x sck cs si so msb 23 1 0 0000000 67 5 4 opcode 10 11 9 81415 13 12 1 msb dxxxxdx x status register in high-impedance 21 at25dn256 ds-25dn256?039b?5/2014 the complete one byte of data must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of the rste bit will not change, and the wel bit in the status register will be reset back to the logical 0 state. figure 11-3. write stat us register byte 2 12. other commands and functions 12.1 read manufacturer and device id identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jede c defined manufacturer id, the vendor specific device id, and the vendor specific extended device information. since not all flash devices are capable of operating at ve ry high clock frequencies, applications should be designed to read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the application can be identified properly. once the identification process is complete, the application can increase the clock frequency to accommodate specific flash devices that are capable of operating at the higher clock frequencies. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device information string length, which will be 00h indicating that no extended device information follows. after the extended device information string length byte is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional.deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 11-4. write status register byte 2 format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x rste x x x x sck cs si so msb 23 1 0 0011000 67 5 4 opcode 10 11 9 81415 13 12 1 msb xxxdxxx x status register in byte 2 high-impedance table 12-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 22 at25dn256 ds-25dn256?039b?5/2014 figure 12-1. read manufacturer and device id 12.2 read id (legacy command) identification information can be read from the device to enable systems to electronically query and identify the device while it is in system. the preferred method for doing so is the jedec standard ?read manufacturer and device id? method described in section 12.1 on page 21 ; however, the legacy read id command is supported on the at25dn256 to enable backwards compatibility to previous generation devices. to read the identification information, the cs pin must first be asserted and the opcode of 15h must be clocked into the device. after the opcode has been clocked in, the device will begin outputting the identification data on the so pin during the subsequent clock cycles. the first byte that will be output will be the manufacturer id of 1fh followed by a single byte of data representing a device code of 65h. after the device code is output, the so pin will go into a high-impedance state; therefore, additional clock cycles will have no affect on the so pin and no data will be output. 2 device id (part 1) 40h 3 device id (part 2) 00h 4 extended device information string length 00h table 12-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for adesto) 0 0 0 1 1 1 1 1 device id (part 1) family code density code 40h family code: 010 (at25dnxxx series) ? density code: 00000 (256-kbit) 0 1 0 0 0 0 0 0 device id (part 2) sub code product version code 00h sub code: 000 (standard series) ? product version:00001 0 0 0 0 0 0 0 0 table 12-1. manufacturer and device id information byte no. data type value sck cs si so 6 0 9fh 8 7 38 opcode 1fh 40h 00h 00h manufacturer id device id byte 1 device i d byte 2 extended device information string length high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits) 23 at25dn256 ds-25dn256?039b?5/2014 deasserting the cs pin will terminate the read id operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data read. figure 12-2. read id (legacy command) 12.3 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offers the ability to place the device into an even lower power consumption state called the deep power-down mode. when the device is in the deep power-down mode, all co mmands including the read status register command will be ignored with the exception of the resume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection me chanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power-cycle. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 12-3. deep power-down 6 & . & 6 6 , 6 2 0 6 % 2 3 & 2 ' ( 0 6 % 0 6 % 0 $ 1 8 ) $ & 7 8 5 ( 5 , ' ' ( 9 , & ( & 2 ' ( + , * + , 0 3 ( ' $ 1 & ( sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd 24 at25dn256 ds-25dn256?039b?5/2014 12.4 resume from deep power-down in order to exit the deep power-down mode and resume nor mal device operation, the resume from deep power-down command must be issued. the resume from deep power-down command is the only command that the device will recognized while in the deep power-down mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power-down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, or if the cs pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the deep power-down mode. figure 12-4. resume from deep power-down 12.5 ultra-deep power-down the ultra-deep power-down mode allows the device to further reduce its energy consumption compared to the existing standby and deep power-down modes by shutting down additional inte rnal circuitry. when the device is in the ultra- deep power-down mode, all commands including the status register read and resume from deep power-down commands will be ignored. since all commands will be ignored, the mode can be used as an extra protection mechanism against inadvertent or unintentional program and erase oper ations. entering the ultra-deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode 79h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will enter the ultra-deep power-down m ode within the maximum time of t eudpd the complete opcode must be clocked in before the cs pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addition, the device will default to the standby mode after a power cycle. the ultra-deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd 25 at25dn256 ds-25dn256?039b?5/2014 figure 12-5. ultra -deep power-down 12.6 exit ultra-deep power-down to exit from the ultra-deep power-down mode, any one of three operations can be performed: chip select toggle the cs pin must simply be pulsed by asserting the cs pin, waiting the minimum necessary t cslu time, and then deasserting the cs pin again. to facilitate simple software development, a dummy byte opcode can also be entered while the cs pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case. after the cs pin has been deasserted, the device will exit from the ultra-deep power-down mode and return to the standby mode within a maximum time of t xudpd if the cs pin is reasserted before the t xudpd time has elapsed in an attempt to start a new operation, then that operation will be ignored and nothing will be performed. figure 12-6. exit ultra-deep power-down (chip select toggle) chip select low by asserting the cs pin, waiting the minimum necessary t xudpd time, and then clocking in the first bit of the next opcode command cycle. if the first bit of the next command is clocked in before the t xudpd time has elapsed, the device will exit ultra deep power down, however the intended operation will be ignored. sck cs si so msb i cc 23 1 0 0 67 5 4 opcode high-impedance ultra-deep power-down mode current active current standby mode current t eudpd 1111001 cs so i cc high-impedance ultra-deep power-down mode current active current standby mode current t xudpd t cslu 26 at25dn256 ds-25dn256?039b?5/2014 figure 12-7. exit ultra-deep power-down (chip select low) power cycling the device can also exit the ultra deep power mode by power cycling the device. the system must wait for the device to return to the standby mode before normal command operations can be resumed. upon recovery from ultra deep power down all internal registers will be at there power-on default state. 12.7 hold the hold pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or erase cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won?t be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pin will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the ho ld mode won?t end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the wel bit in t he status register back to the logical ?0? state. figure 12-8. hold mode cs so i cc high-impedance ultra-deep power-down mode current active current t xudpd sck cs hold hold hold hold 27 at25dn256 ds-25dn256?039b?5/2014 12.8 reset in some applications, it may be necessary to prematurely terminate a program or erase operation rather than wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete normally. the reset command allows a program or erase operation in progress to be ended abruptly and returns the device to an idle state. since the need to reset the device is immediate, the write enable command does not need to be issued prior to the reset command. therefore, the reset command operates i ndependently of the state of the wel bit in the status register. the reset command can be executed only if the command has been enabled by setting the reset enabled (rste) bit in the status register to a logical 1 using write status register byte 2 command 31h. this command should be entered before a program command is entered. if the reset command has not been enabled (the rste bit is in the logical 0 state), then any attempts at executing the reset command will be ignored. to perform a reset, the cs pin must first be asserted, and then the opcode f0h must be clocked into the device. no address bytes need to be clocked in, but a confirmation byte of d0h must be clocked into the device immediately after the opcode. any additional data clocked into the device afte r the confirmation byte will be ignored. when the cs pin is deasserted, the program operation currently in progress will be terminated within a time of t swrst . since the program or erase operation may not complete before the device is reset, the contents of the page being programmed or erased cannot be guaranteed to be valid. the reset command has no effect on the states of the configuration register or rste bit in the status register. the wel however, will be reset back to its default state. the complete opcode and confirmation byte must be clocked into the device before the cs pin is deasserted, and the cs pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no reset operation will be performed. figure 12-9. reset 13. electrical specifications sck cs si so msb 23 1 0 1111000 67 5 4 opcode confirmation byte in 10 11 9 81415 13 12 0 msb 1101000 0 high-impedance 13.1 absolute maximum ratings* temperature under bias. . . . . . . . -55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability. storage temperature . . . . . . . . . . -65 ? c to +150 ? c all input voltages ? (including nc pins) ? with respect to ground . . . . . . . . . .-0.6v to +4.1v all output voltages ? with respect to ground . . . . . .-0.6v to v cc + 0.5v 28 at25dn256 ds-25dn256?039b?5/2014 13.3 dc characteristics notes: 1. typical values measured at 3.0v @ 25 c for the 2.3v to 3.6v range. 13.2 dc and ac operating range at25dn256 operating temperature (case) ind. -40 ? c to 85 ? c v cc power supply 2.3v to 3.6v symbol parameter condition 2.3v to 3.6v units min typ max i udpd ultra-deep power-down current all inputs at 0v or v cc 0.35 1 a i dpd deep power-down current cs , hold , wp = v ih ? all inputs at cmos levels 5 15 a i sb standby current cs , hold , wp = v ih ? all inputs at cmos levels 25 40 a i cc1 (1) active current, low power read (03h, 0bh) operation f = 1mhz; i out = 0ma 6 9 ma f = 20mhz; i out = 0ma 7 10 ma i cc2 (1) ? active current, ? read operation f = 50mhz; i out = 0ma 7 11 ma f = 85mhz; i out = 0ma 7 12 ma i cc3 (1) active current, ? program operation cs = v cc 10 15 ma i cc4 (1) active current, ? erase operation cs = v cc 12 18 ma i li input load current all inputs at cmos levels 1 a i lo output leakage current all inputs at cmos levels 1 a v il input low voltage v cc x 0.3 v v ih input high voltage v cc x 0.7 v v ol output low voltage i ol = 1.6ma; v cc = 2.3v 0.4 v v oh output high voltage i oh = -100a v cc - 0.2v v 29 at25dn256 ds-25dn256?039b?5/2014 ? 13.4 ac characteristics - m aximum clock frequencies symbol parameter 2.3v to 3.6v units min typ max f clk maximum clock frequency for all operations ? (excluding 0bh opcode) 104 mhz f rdlf maximum clock frequency for 03h opcode (read array ? low frequency) 33 mhz f rddo maximum clock frequency for 3b opcode 50 mhz 13.5 ac characteristics ? all other parameters symbol parameter 2.3v to 3.6v units min typ max t clkh clock high time 4 ns t clkl clock low time 4 ns t clkr (1) clock rise time, peak-to-peak (slew rate) 0.1 v/ns t clkf (1) clock fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chip select high time 30 ns t csls chip select low setup time (relative to clock) 5 ns t cslh chip select low hold time (relative to clock) 5 ns t cshs chip select high setup time (relative to clock) 5 ns t cshh chip select high hold time (relative to clock) 5 ns t ds data in setup time 2 ns t dh data in hold time 1 ns t dis (1) output disable time 6 ns t v output valid time 6 ns t oh output hold time 0 ns t hls hold low setup time (relative to clock) 5 ns t hlh hold low hold time (relative to clock) 5 ns t hhs hold high setup time (relative to clock) 5 ns t hhh hold high hold time (relative to clock) 5 ns t hlqz (1) hold low to output high-z 6 ns t hhqx (1) hold high to output low-z 6 ns t wps (1)(2) write protect setup time 20 ns t wph (1)(2) write protect hold time 100 ns t edpd (1) chip select high to deep power-down 2 s 30 at25dn256 ds-25dn256?039b?5/2014 notes: 1. not 100% tested (value guaranteed by design and characterization). 2. only applicable as a constraint for the write status register command when bpl = 1. ? note: 1. maximum values indicate worst-case performance after 100,000 erase/program cycles. 2. not 100% tested (value guaranteed by design and characterization). t eudpd . chip select high to ultra deep power-down 3 s t swrst software reset time 50 s t cslu minimum chip select low to exit ultra deep power-down 20 ns t xudpd exit ultra deep power-down time 70 s t rdpd (1) chip select high to standby mode 8 s 13.6 program and er ase characteristics symbol parameter 2.3v-3.6v min typ max units t pp (1) page program time (256 bytes) 1.5 3.0 ms t bp byte program time 8 s t pe page erase time 6 25 ms t blke (1) block erase time 4 kbytes 40 50 ms 32 kbytes 320 400 t chpe (1)(2) chip erase time 320 400 ms t otpp (1) otp security register program time 400 950 s t wrsr (2) write status register time 20 40 ms 13.7 power-up conditions symbol parameter min max units t vcsl minimum v cc to chip select low time 70 s t puw power-up device delay before program or erase allowed 5 ms v por power-on reset voltage 1.6 2.2 v 13.5 ac characteristics ? all other parameters symbol parameter 2.3v to 3.6v units min typ max 31 at25dn256 ds-25dn256?039b?5/2014 13.8 input test waveforms and measurement levels 13.9 output test load 14. ac waveforms figure 14-1. serial input timing figure 14-2. serial output timing ac driving levels ac measurement level 0.1v cc v cc /2 0.9v cc t r , t f < 2 ns (10% to 90%) device under test 30pf cs si sck so msb high-impedance msb lsb t csls t clkh t clkl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t clkh t clkl t dis t v t oh 32 at25dn256 ds-25dn256?039b?5/2014 figure 14-3. wp timing for write status register command when bpl = 1 ? figure 14-4. hold timing ? serial input figure 14-5. hold timing ? serial output ? wp si sck so 000 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode cs si sck so t hhh t hls t hlh t hhs hold high-impedance cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx 33 at25dn256 ds-25dn256?039b?5/2014 15. ordering information 15.1 ordering code detail note: the shipping carrier option code is not marked on the devices. a t 2 5 d 2 5 s s h b 6? ? n designator product family device density 256 = 256-kilobit package option ss = 8-lead, 0.150" wide soic ma = 8-pad, 2 x 3 x 0.6 mm udfn xm = 8-lead tssop device grade h = green, nipdau lead finish, industrial temperature range (-40c to +85c) shipping carrier option b = bulk (tubes) t = tape and reel f voltage code f = 2.3v to 3.6v ordering code package lead finish operating voltage max. freq. (mhz) operation range AT25DN256-SSHF-B at25dn256-sshf-t 8s1 nipdau 2.3v to 3.6v 104 industrial (-40c to +85c) at25dn256-mahf-t 8ma3 at25dn256-xmhf-b 8x at25dn256-xmhf-t package type 8s1 8-lead, 0.150" wide, plastic gull wi ng small outline package (jedec soic) 8ma3 8-pad, 2 x 3 x 0.6mm, thermally enhanced plastic ultra thin dual flat no lead package (udfn) 8x 8-lead, thin small outline package 34 at25dn256 ds-25dn256?039b?5/2014 16. packaging information 16.1 8s1 ? jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? ? e e 1 1 n n top view t o p v i e w c c e1 e 1 end view a a b b l l a1 a 1 e e d d side view s i d e v i e w package drawing contact: contact@adestotech.com ? 8s1 f 5/19/10 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb 35 at25dn256 ds-25dn256?039b?5/2014 16.2 8ma3 ? udfn title drawing no. gpc rev. package drawing contact: contact@adestotech.com ? 8ma3 ycq a 8ma3, 8-pad, 2 x 3 x 0.6 mm body, 0.5 mm pitch, 1.6 x 0.2 mm exposed pad, saw singulated thermally enhanced plastic ultra thin dual flat no lead package (udfn/uson) common dimensions (unit of measure = mm) symbol min nom max note a 0.45 ? 0.60 a1 0.00 ? 0.05 b 0.20 ? 0.30 d 1.95 2.00 2.05 d2 1.50 1.60 1.70 e 2.95 3.00 3.05 e2 0.10 0.20 0.30 e ? 0.50 ? l 0.40 0.45 0.50 l3 0.30 ? 0.40 ccc ? ? 0.05 eee ? ? 0.05 8/8/08 notes: 1. all dimensions are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.05 mm. 3. warpage shall not exceed 0.05 mm. 4. package length/package width are considered as special characteristic. 5. refer to jede mo-236/mo-252 1 4 8 5 b e2 d2 8x c 0.10 mm b a r0.10 l3 0.10 ref. e 1.50 ref. r0.125 d 1 4 pin 1 id e 5 b a a1 a 0.127 ref. c c eee ccc 8x c 23 6 7 8 l // 36 at25dn256 ds-25dn256?039b?5/2014 16.3 8x-tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. h 8x e 12/8/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1 package drawing contact: contact@adestotech.com ? 37 at25dn256 ds-25dn256?039b?5/2014 17. revision history revision level ? release date history a ? january 2014 initial release b ? may 2014 removed ?all inputs (sck, cs , wp and hold ) are guaranteed by design to be 5v tolerant from table 13-3. updated ac and dc characteristics. removed tray carrier option from dfn parts. changed datasheet status to preliminary. corporate office california | usa adesto headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: (+1) 408.400.0578 email: contact@adestotech.com ? 2014 adesto technologies. all rights reserved. / rev.: ds-25dn256?039b?5/2014 disclaimer: adesto technologies corporation makes no warranty for the use of its products, other than those expressly contained in the company's standard warranty which is detailed in adesto's terms and conditions located on the company's web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no lic enses to patents or other intellectual property of adesto are granted by the company in connection with the sale of adesto products, expressly or by implication. adesto's products are not authorized for u se as critical components in life support devices or systems. adesto ? , the adesto logo, cbram ? , and dataflash ? are registered trademarks or trademarks of adesto technologies. all other marks are the property of their respective owners. mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: adesto technologies: ? at25dn256-sshfgp-t? at25dn256-sshfgp-b? at25dn256-mahfgp-t? at25dn256-xmhfgp-t? at25dn256- xmhfgp-b |
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